Switching time optimizer for soft switching of an isolated converter

ABSTRACT

An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the T D(L-H)  optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the T D(H-L)  optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the T DM  optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

RELATED APPLICATION

This application claims the benefit of U.S. provisional patent application No. 62/480,881 filed Apr. 3, 2017, the contents of which are incorporated by reference as though fully re-written herein.

TECHNICAL FIELD

This disclosure relates generally to switching optimization in power management devices and more specifically to zero voltage switching (ZVS) of an active clamp flyback converter.

BACKGROUND

Flyback converters convert a first alternating current (AC) level or a first direct current (DC) level to a second DC current level. Flyback converters often have two or more circuits that are galvanically isolated from one another. Galvanic isolation means that current cannot flow directly between the circuits. However, energy can still be transferred between the different portions of the circuit through other means such as, for example, capacitance, induction, or electromagnetism.

Flyback converters commonly use transformers to galvanically isolate different circuits within the flyback converter. Transformers transfer energy through a coupling created by the magnetic flux between a first and a second winding of the transformer. Depending on the winding ratio of the transformer, a first voltage may be increased, decreased, or in some applications remain the same.

The transformer effectively splits the flyback converter into two circuits, a primary circuit and a secondary circuit. When the primary side circuit is ON, current flows through the windings of the transformer in the primary circuit. The flow of current through the windings creates a magnetic flux that induces a voltage with a first polarity across the transformer windings of the secondary circuit. Energy is stored in the magnetic flux between the transformer windings of the primary circuit and the transformer windings of the secondary circuit. The secondary circuit will have a polar circuit mechanism, such as a diode, that will prevent energy from flowing as electric current through the secondary circuit transformer windings when the voltage across the polar mechanism is reversed biased. When the primary circuit is OFF the polarity of the voltage across the secondary winding is reversed and the energy stored in the magnetic flux between the primary circuit transformer windings and the secondary circuit transformer windings will flow into the secondary circuit as electric current. However, not all of the energy stored in the magnetic flux is transferred to the secondary circuit. Some energy is stored in the primary circuit by a magnetizing inductance of the primary circuit, and some energy is stored in the primary circuit as the result of a leakage inductance of the primary circuit. These inductances create electric currents in the primary circuit even when the primary circuit is OFF.

The ON and OFF states of the primary circuit can be controlled by a control switch disposed between an input of the primary circuit and its ground. The input of the converter is connected to a first terminal of the transformer, and the control switch is connected to the other terminal. By controlling the connection to ground using the switch, current flowing through the primary circuit transformer windings from the input is controlled. The switching voltage at the node that connects the transformer to the control switch will alternate between a high-voltage level and a value close to 0V, when the control switch changes the state.

When the connection of the clamping circuit between the switching node and ground or between the switching node and input source is controlled by a clamping switch in series with the clamping capacitor, the clamp circuit is considered active. The active clamp circuit can eliminate both switching loss and clamping loss of the flyback converter. The flow of current at various switching states is described in detail in R. Watson, F. C. Lee, G. C. Hua, “Utilization of an active-clamp circuit to achieve soft switching in flyback converter,” IEEE Trans., 1994 which is hereby incorporated by reference in its entirety.

When the primary circuit is turned off, the energy stored in the primary circuit as a result of the magnetizing and leakage inductance will commute to a clamp circuit. The clamp circuit may connect between the node that connects the transformer to the control switch and ground, or between the switch node and the input source.

When the clamping circuit is formed by a diode rectifier in series with a transient voltage suppressor (TVS), two power losses impair the efficiency of the power convertor, especially when the control switch is operated at high switching frequency. These power losses are switching loss and clamping loss. Switching loss is governed by equation (1) below.

$P_{Csw} = {\frac{1}{2}{C_{sw}\left( {V_{in} - {NV}_{0}} \right)}^{2}f_{sw}}$ Equation (1) explains that the power dissipated by the control switch, P_(Csw), is equal to half of the square of the difference between the input voltage, V_(in), and the product of the winding ratio, N, and the output voltage, V₀, multiplied by the resonate switch node capacitance, C_(sw), and the switching frequency, f_(sw). Clamping loss is governed by equation (2) below.

$P_{clamp} = {\frac{V_{clamp}}{V_{clamp} - {NV}_{0}}\frac{1}{2}L_{k}i_{m{( + )}}^{2}f_{sw}}$ Equation (2) explains that the power dissipated by the clamp circuit, P_(clamp), is equal to half of the ratio of the clamp voltage on the TVS, V_(clamp), to the difference between the clamp voltage and the product of the winding ratio, N, and the output voltage, V₀, multiplied by the product of the leakage inductance, L_(k), the switching frequency, f_(sw), and the square of the positive peak magnetizing current, i_(m(+)).

As can be seen from observing equations (1) and (2) above, the clamping loss, P_(clamp), and the switching loss, P_(Csw), are directly proportional to the switching frequency, f_(sw). As such, clamping and switching losses are bottlenecks from high frequency operation of the flyback converters using this conventional clamping circuit.

The power losses explained in equations (1) and (2) above can be minimized by controlling the ON and OFF state of the control switch and the clamp switch in accordance with zero voltage switching (ZVS) conditions. ZVS can be achieved when the inequality in equation (3) below is true.

${\frac{1}{2}L_{m}i_{m{( - )}}^{2}} \geq {\frac{1}{2}C_{sw}V_{sw}^{2}}$ Equation (3) explains that zero voltage switching can be achieved when half of the product of the magnetizing inductance, L_(m), and the square of the negative peak magnetizing current, i_(m(−)), is greater than or equal to half of the product of the resonant switching node capacitance, C_(sw), and the square of the switching node voltage, V_(sw).

In order to control the ON and OFF states of the control and clamp switches such that ZVS conditions are met, the length of the dead time between turning the control switch OFF and the clamp switch ON, T_(D(L-H)); the length of the time the clamp switch is ON, T_(DM); and the length of dead time between turning the clamp switch OFF and the control switch ON, T_(D(H-L)), must be properly controlled.

The goal of controlling T_(D(L-H)) is to properly control the ZVS timing of the clamping switch. Optimally, T_(D(L-H)) may be controlled by equation (4) below.

$T_{D{({L - H})}} = {\frac{C_{sw}}{i_{m{( + )}}}\left( {V_{in} + {NV}_{0}} \right)}$ Equation (4) explains that T_(D(L-H)) is directly proportional to the switching node capacitance, C_(sw), multiplied by the sum of the input voltage, V_(in), and the product of the winding ratio, N, and the output voltage, V₀. Equation (4) further explains that T_(D(L-H)) is inversely proportional to the positive peak current, i_(m(+)).

The switching node capacitance, C_(sw), represents the total capacitive load of the switching node on the primary circuit, which includes the nonlinear junction capacitance of control switch and clamping switch. Variation of the switching node capacitance, C_(sw), is affected by the capacitance nonlinearity and the manufacturing tolerance. The input voltage, V_(in), range varies widely due to the universal AC line's ranging from 90 Vac to 265 Vac. The voltage output, V₀, range also varies widely from 5V to 20V to power personal electronic devices, and i_(m(+)) is modulated for the output voltage, V₀, regulation of the wide output load range. Because Equation (4) is sensitive to those parameter changes and operating conditions, controller design based on Equation (4) is difficult.

For example, C_(sw), has non-linear components. Taking these non-linearities into account, the optimal T_(D(L-H)) is approximated by Equation (5) below.

$T_{D{({L - H})}} \approx {{\frac{2C_{oss\_ Small}}{i_{m{( + )}}}\left( {V_{in} + {NV}_{0} - V_{th}} \right)} + {\frac{2C_{oss\_ Big}}{i_{m{( + )}}}V_{th}}}$ Equation (5) accounts for the non-linear nature of C_(sw) by approximating T_(D(L-H)) using its components, C_(oss_Small) and C_(oss_Big). V_(th) is the drain-to-source voltage of the control switch where the junction capacitance transitions from a large capacitance value to a small capacitance value.

If the clamping switch is turned ON before the optimal time period for T_(D(L-H)) expires, ZVS is lost for the clamping switch. This will result in a hard-switching event. Hard-switching causes large power loss and creates a large amount of electromagnetic interference.

For any duration of time that the clamping switch remains OFF after the optimal time period for T_(D(L-H)) expires, power losses across the body diode of the clamping switch will occur, since the body diode conduction time is extended.

The goal of controlling T_(DM) is to properly control the ON time of the control switch. T_(DM) can be optimally calculated using equation (6) below.

$T_{DM} = {\frac{L_{m}i_{m{( + )}}}{{NV}_{0}} + {{\tan\left( \theta_{2} \right)}\sqrt{L_{m}C_{sw}}}}$ ${{where}\mspace{14mu} T_{LC}} = {{2\pi\sqrt{L_{m}C_{sw}}\mspace{14mu}{and}\mspace{14mu}\theta_{2}} = {\cos^{- 1}\frac{{NV}_{0}}{V_{in}}}}$

Equation (6) explains that the optimal value of T_(DM) is equal to the ratio of the product of the magnetizing inductance, L_(m), and the positive peak magnetizing current, i_(m(+)), to the product of the winding ratio, N, and the output voltage, V₀, added to the product of tan (θ₂) and the square root of the product of the magnetizing current, L_(m), and the resonant switching node capacitance, C_(sw).

If T_(DM) is not long enough, the negative peak magnetizing current will not be large enough, causing the switching node voltage, V_(sw), to be greater than zero when T_(D(H-L)) expires. This will result in loss of ZVS of the control switch, causing switching losses to increase.

If T_(DM) is too long, the negative peak magnetizing current will become too large. This results in a larger conduction loss because the root mean square (RMS) of the magnetizing current is larger, causing more current flow into the clamping and control switches as well as the transformer. This also results in a larger power loss on the magnetic core of the transformer because higher peak-to-peak magnetizing current increases the flux density.

The goal of controlling T_(D(H-L)) is to properly control the ZVS timing of the control switch. T_(D(H-L)) can be optimally controlled by equation (7) below.

$T_{{D{({H - L})}}{OPT}} = {\frac{\left( {\pi - \theta_{2}} \right)}{2\pi}T_{LC}}$ ${{Where}\mspace{14mu} T_{LC}} = {{2\pi\sqrt{L_{m}C_{sw}}\mspace{14mu}{and}\mspace{14mu}\theta_{2}} = {\cos^{- 1}\frac{{NV}_{0}}{V_{in}}}}$

Equation (7) explains that the optimal value of T_(D(H-L)OPT) is equal to the product of the capacitive-inductive time constant, T_(LC), and the quotient of

$\frac{\left( {\pi - \theta_{2}} \right)}{2\pi}.$

If T_(D(H-L)) is too long, the switching node voltage, V_(sw), will resonate above 0V again after the voltage reaches 0V and cause the control switch to be turned ON when the switching node voltage, V_(sw), is a non-zero value. This results in a loss of ZVS for the control switch and causes power losses.

If T_(D(H-L)) is too short, the negative peak magnetizing current has to be increased to achieve ZVS of control switch within the limited time. This results in a large conduction loss because the root mean square (RMS) of the magnetizing current is larger, causing more current to flow into the clamping and control switches as well as the transformer. Besides, this also results in a large power loss on the magnetic core of the transformer because higher peak-to-peak magnetizing current increases the flux density.

A first prior art solution addresses the power losses associated with T_(D(L-H)), T_(DM), and T_(D(H-L)), discussed above, by fixing T_(D(L-H)) and T_(D(H-L)) to a set length of time and creating a duty cycle dependent T_(DM) using a fixed switching frequency. In this solution, the two fixed dead time settings cannot provide optimal design over the parameter variations, so the related power loss issues cannot be resolved. The duty cycle of the pulse width modulated signal controlling T_(DM) is operated at a constant frequency condition through the input and load range. However, because the frequency of the PWM signal is fixed, the power losses when utilizing this prior art solution are still substantial. For example, the fixed frequency operation keeps T_(DM) the same between heavier and lighter output load conditions, so the fixed T_(DM) will unnecessarily increase the negative peak magnetizing current, i_(m(−)), at a lighter load. This will result in too much circulating energy in the circuit for ZVS, so light load efficiency is impaired. Similarly, if the frequency remains the same for high and low input voltage, V_(in), conditions, the negative peak magnetizing current will be too low for low line, resulting in hard switching of the control switch.

A second prior art solution attempts to use complex mathematical equations that use predicted values of the magnetizing inductance, L_(m), and the resonant switching node capacitance, C_(sw), to individually solve for T_(D(L-H)), T_(DM), and T_(D(H-L)). However, the use of these equations increases the cost of the microcontroller unit (MCU) needed to solve for these values. Most importantly, the values generated are sensitive to component tolerance because they are based on the magnetizing inductance, L_(m), and the resonant switching node capacitance, C_(sw). When the actual value is deviated away from the predetermined value in MCU, the calculated result will be offset from the optimal timing, and causes the power loss increase.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example active clamp flyback converter.

FIG. 2 illustrates a schematic block diagram of a control system for controlling ZVS of an active clamp flyback converter.

FIG. 3 illustrates a schematic block diagram of the analog tuner of the T_(DM) optimizer of FIG. 2.

FIG. 4 illustrates a schematic block diagram of the T_(D(H-L)) optimizer of FIG. 2.

FIG. 5 illustrates a schematic block diagram of the T_(D(L-H)) optimizer of FIG. 2.

FIG. 6 illustrates a timing relationship between illustrates T_(D(H-L)), T_(DM), T_(D(H-L)), the switching node voltage 114, PWMH signal 128, and the PWML signal 130.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the disclosure. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted to facilitate a less obstructed view of these various embodiments. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above, except where different specific meanings have otherwise been set forth herein.

DETAILED DESCRIPTION

The following detailed embodiments describe an apparatus for optimally performing zero voltage switching (“ZVS”) of an active clamp flyback converter. A first timing circuit acts as a T_(D(L-H)) optimizer and receives a signal detecting the zero-crossing of the auxiliary winding voltage directly in order to adaptively vary the dead time. A second timing circuit acts as a T_(D(H-L)) optimizer to adaptively vary the dead time with a simple piece-wide linear function, which is an approximation of the complex optimal equation described above. A third timing circuit acts as a T_(DM) optimizer and includes a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of the switching node voltage so that the correct amount of negative magnetizing current is generated to improve zero voltage switching. Together these three timing circuits work to reduce or avoid the need of computing complex calculations through a microcontroller unit (MCU) to solve the optimal control values and compensate the parameter variations based on direct voltage sensing and online adjustment for every switching cycle.

Referring now to the figures, FIG. 1 illustrates an example of an active clamp flyback converter circuit. The active clamp flyback converter circuit has a primary side 100 and a secondary side 151. The primary side 100 takes an input voltage V_(in) 102 that induces current I_(pri) 104 to flow through primary side windings 106 when the control switch Q_(L) 108 is ON. The control switch Q_(L) 108 may be any switch that can be controlled by a pulse width modulated signal. For example, the control switch Q_(L) 108 may be a metal oxide semiconductor field effect transistor (“MOSFET”) or a gallium nitride field effect transistor (“GaN FET”). The PWML signal 130 is a pulse width modulated signal that turns the control switch 108 ON and OFF through a half-bridge gate driver 140. The PWML signal 130 will turn control switch Q_(L) 108 ON and OFF based on the logic state of the PWML signal 130. For example, if the PWML signal 130 is logic HIGH the control switch Q_(L) 108 will be ON, and if the PWML signal 130 is logic LOW the control switch Q_(L) 108 will be OFF. The half bridge gate driver 140 can convert the logic state of PWML to an appropriate driving voltage between the gate and the source of the control switch Q_(L) 108. As will be described in detail in the description of FIG. 2, the timing of the state change of the PWML signal 130 depends on T_(D(H-L)).

Because the clamp current i_(clamp) 118 is bi-directional when the clamp switch Q_(H) 110 is ON, the voltage of the clamp capacitor 116 is applied across the magnetizing inductance 122 to create a negative magnetizing current for ZVS. The clamp switch Q_(H) 110 may be any switch that can be controlled by a pulse width modulated signal. For example, the clamp switch Q_(H) 110 may be a MOSFET or a GaN FET. The PWMH signal 128 is a pulse width modulated signal that turns the clamp switch Q_(H) 110 ON and OFF through a half-bridge gate driver 140. The PWMH signal 128 will turn clamp switch Q_(H) 110 ON and OFF based on the logic state of the PWMH signal 128. For example, if the PWMH signal 128 is logic HIGH the clamp switch Q_(H) 110 will be ON, and if the PWMH signal 128 is logic LOW the clamp switch Q_(H) 110 will be OFF. It can also be the case that if the PWMH signal 128 is logic HIGH, the control switch Q_(H) 110 will be OFF, and if the PWMH signal 128 is logic LOW, the control switch Q_(H) 108 will be ON. The half-bridge gate driver 140 level shifts from the logic state of PWMH to an appropriate driving voltage between the gate and the source of the clamp switch Q_(H) 110. As will be described in detail in the description of FIG. 2, the timing of the state change of the PWMH signal 128 depends on T_(D(L-H)) and T_(DM).

The primary side 100 of the active clamp flyback converter has a leakage inductance L_(k) 120 and a magnetizing inductance L_(m) 122. The leakage inductance L_(k) 120 and the magnetizing inductance L_(m) 122 are not physical circuit elements; rather they illustrate inductances introduced into the primary side 100 by the primary side windings 106 of the transformer. The magnetizing current i_(m) 124 is the current introduced into the primary side 100 by the magnetizing inductance L_(m) 122.

Similarly, the primary side 100 of the active clamp flyback converter has a resonant switching node capacitance C_(sw) 112 at the switching node 144. The resonant switching node capacitance C_(sw) 112 is not a physical circuit element itself. Instead, the resonant switching node capacitance C_(sw) 112 is dominated by the sum of the parasitic junction capacitance of the clamp switch Q_(H) 110 and the control switch Q_(L) 108 of the primary side 100.

The secondary side 151 has a secondary side winding 101 and a polar element 111, such as a diode, that controls the flow of the current i_(D) 103 through the secondary side 151 by acting as an output rectifier. The secondary side 151 also has an output filter capacitor 109 with its equivalent series resistance 107 acting to reduce the output switching ripple of the output voltage V₀ 113 across the resistive output load 105.

FIG. 2 illustrates a control circuit for driving the clamp switch and the control switch of an active clamp flyback converter, such as the active clamp flyback converter circuit illustrated in FIG. 1, according to optimized values for T_(D(H-L)), T_(D(L-H)), and T_(DM) using a first timing circuit corresponding to a T_(D(H-L)) optimizer 205, a second timing circuit corresponding to a T_(D(L-H)) optimizer 210, and a third timing circuit corresponding to a T_(DM) optimizer 204. The voltage divider 200 senses an auxiliary winding voltage V_(aux) 220 across an auxiliary winding 201. The auxiliary winding is a separate winding coupled with the primary winding 106 and the secondary winding 101. The voltage divider 200 divides the auxiliary voltage across the resistors 200 a and 200 b. An input voltage, such as input voltage V_(in) 102, is sensed by the V_(in) sensing circuit 203 from a voltage determined by the voltage divider 200. Likewise, a clamped primary voltage, NV₀, of the primary side winding is sensed by the NV₀ sensing circuit 202.

The V_(in) sensing circuit 203 may be coupled to both the first timing circuit such as the T_(D(H-L)) optimizer 205 and the third timing circuit such as the T_(DM) optimizer 204. The T_(D(H-L)) optimizer 205 and the T_(DM) optimizer are coupled to each other as well as to the ZVS sensing circuit 206. The ZVS sensing circuit 206 takes the switching node voltage V_(sw) 114 of the switching node 144 as an input and outputs a zero voltage detection (ZVD) to both the T_(D(H-L)) optimizer 205 and the T_(DM) optimizer 204. The T_(D(H-L)) optimizer 205 takes an analog feedforward signal from V_(in) sensing circuit 203 and the ZVD signal from the ZVS sensing circuit 206 as an input and outputs a time-out (TIO) logic signal 209 to the T_(DM) optimizer 204 and outputs a logic signal to set an SR flip flop 208. The T_(D(H-L)) optimizer 205 will be described below with reference to FIG. 4, and the T_(DM) optimizer 204 will be described below with reference to FIG. 3.

The control system of FIG. 2 may further include a feedback compensation circuit 226, a comparator 212, and an SR flip-flop 208. The SR flip-flop 208 acts as a state register having a high state and a low state corresponding to a logic HIGH state and a logic LOW state. The feedback compensation circuit 226 is coupled to the comparator 212. The comparator 212 and the T_(D(H-L)) optimizer 205 are coupled to the SR flip-flop 208. The comparator 212 takes, as input, the output of the feedback compensation circuit 226 and a S_(n) ramp signal 214. The S_(n) ramp signal 214 is a current-sense signal proportional to the switching current flowing through the control switch Q_(L) 108. The S_(n) ramp signal 214 may be determined by, for example, using a current-sense resistor or a current-sense transformer in series with the source pin of the control switch Q_(L) 108. If a value of the feedback compensation voltage V_(c) 224 is lower than the value of the S_(n) ramp signal 214, the comparator 212 outputs logic HIGH. Otherwise, the comparator 212 outputs logic LOW. The output of the comparator 212 controls the reset function of the SR flip-flop 208. The output of the SR flip-flop 208 provides a pulse width modulated signal such as the PWML signal 130. When a logic HIGH value is received by the SR flip-flop 208 from the comparator 212, the PWML signal 130 will remain logic low until a logic HIGH value is received from the T_(D(H-L)) optimizer 205. The logic state of the T_(D(H-L)) optimizer 205 controls the set function of the SR flip-flop 208. When the T_(D(H-L)) optimizer 205 outputs logic HIGH, the output of the PWML signal 130 will remain logic HIGH until the comparator 212 outputs logic HIGH.

The control system of FIG. 2 may further include a second timing circuit such as the T_(D(L-H)) optimizer 210, a summing node 222, a comparator 216, and an SR flip-flop 207. The SR flip-flop 207 acts as a state register having a high state and a low state corresponding to a logic HIGH state and a logic LOW state. The T_(D(L-H)) optimizer 210 will be described in detail below with reference to FIG. 5. The feedback compensation circuit 226 and the T_(DM) optimizer 204 are coupled to the summing node 222. The summing node 222 is coupled to the comparator 216. The comparator 216 and the T_(D(L-H)) optimizer 216 are coupled to the SR flip-flop 207. The summing node 222 sums the output compensation voltage V_(c) 224 with the voltage output 221 from the T_(DM) optimizer 204. The comparator 216 receives as input the summed voltage from the summing node 222 and an S_(f) ramp signal 218. The S_(f) ramp signal is generated from the output from the NV₀ sensing circuit 202 and the PWMH signal 128 by a S_(f) ramp generating circuit 228 and output to the comparator 216. The slope of the S_(f) ramp signal 218 will follow the change of output voltage 113 when the PWMH signal 128 is HIGH. When the value of the S_(f) ramp signal 218 is greater than the summed voltage output from the summing node 222 the comparator 216 outputs logic HIGH. Otherwise, the comparator 216 outputs logic LOW. The output of the SR flip-flop 208 provides a pulse width modulated signal such as the PWMH signal 128. The output of the comparator 216 controls the reset function of the SR flip flop 207. When the comparator 216 outputs logic HIGH, the PWMH signal 128 remains logic LOW until the SR flip flop 207 is set. The T_(D(L-H)) optimizer 210 controls the set function of the SR flip-flop 207. The T_(D(L-H)) optimizer 210 is coupled to the SR flip-flop 208 and takes as input a pulse width modulated signal, such as the PWML signal 130, and the auxiliary voltage V_(aux) 220. When the T_(D(L-H)) optimizer 210 outputs logic HIGH, the PWMH signal 128 remains logic HIGH until the comparator 216 outputs logic HIGH. FIG. 6 illustrates the relationship between T_(D(H-L)), T_(DM), T_(D(H-L)), the switching node voltage 114, PWMH signal 128, and the PWML signal 130.

FIG. 3 illustrates a schematic block diagram of the T_(DM) optimizer 204. The T_(DM) optimizer 204 has at least a tuning polarity and speed control circuit 300 and a charge pump circuit 301. The tuning polarity and speed control circuit 300 is coupled to the ZVS sensing circuit 206 and the T_(D(H-L)) optimizer circuit 205 via a logic circuit 305. Within the tuning polarity and speed control circuit 300, the logic circuit 305 is also coupled to an SR flip-flop 310, which is coupled to AND gates 325 and 330. The AND gates 325 and 330 are further coupled to the one-shot circuit 320, and the one-shot circuit 320 is coupled to a counter circuit 315. When the T_(D(H-L)) optimizer circuit 205 outputs a timeout (“TIO”) logic signal 209 as a logic HIGH value before the ZVS sensing circuit 206 outputs a ZVD as a logic HIGH value, PWML signal 130 will become logic HIGH. At the same time, the logic circuit 305 will control the SR flip-flop 310 to output logic HIGH to the AND gate 325. Then, at the falling edge of the PWML signal 130, the one-shot circuit 320 will generate a short logic HIGH pulse that will cause the AND gate 325 to close a charging switch Q_(up) 337 for a short time by outputting a short logic HIGH pulse. When the charging switch Q_(up) 337 is closed, a charge current source 335 of the charge pump circuit 301 flows to the tuning capacitor 350 increasing the voltage across the tuning capacitor and the ΔV_(c) value 221.

When the T_(D(H-L)) optimizer circuit 205 outputs the TIO logic signal 209 as a logic LOW value before the ZVS sensing circuit 206 outputs a ZVD as a logic HIGH value, PWML signal 130 will become logic HIGH. At the same time, the logic circuit 305 will control the SR flip-flop 310 to output logic HIGH to AND gate 330. Then, at the falling edge of the PWML signal 130, the one-shot circuit 320 will generate a short logic HIGH pulse that will cause the AND gate 330 to close a charging switch Q_(Dn) 338 for a short time by outputting a short logic HIGH pulse. When the charging switch Q_(Dn) 338 is closed, a discharge current source 340 of the charge pump circuit 301 flows to ground from the tuning capacitor 350, decreasing the voltage across the tuning capacitor 350 and ΔV_(c) value 221.

The charge pump circuit 301 has a tuning capacitor 350 coupled to two switches, Q_(up) 337 and Q_(Dn) 338. When Q_(up) 337 is closed, a charge current source 335 flows onto the tuning capacitor 350 and increases the ΔV_(c) voltage 221 across it. When Q_(Dn) 338 is closed, a discharge current source 340 flows off of the tuning capacitor 350 and decreases the ΔV_(c) voltage 221 across it. For example, the voltage across the tuning capacitor 350 of the charge pump circuit 301 is determined in every switching cycle based on a racing condition between the occurrence of the zero-voltage detection (ZVD) condition of the switching node voltage 114 as determined by the ZVS sensing circuit 206 and a logic HIGH event of the time-out (TIO) condition as determined by T_(D(H-L)) optimizer 205. If switching node voltage 114 reaches to 0V (ZVD output in a logic HIGH state) and the TIO logic signal 209 output from the T_(D(H-L)) optimizer 205 is in a logic LOW state, ΔV_(c) value 221 output from the charge pump circuit 301 is decreased in the next switching cycle, in order to shorten T_(DM). On the other hand, if switch node voltage 114 did not reach 0V (ZVD output in a logic LOW state) before the TIO logic signal 209 transitioned into a logic HIGH state, the ΔV_(c) value 221 output increases in the next switching cycle, in order to extend T_(DM).

The V_(in) sense circuit 203 provides an input feedforward signal to the ΔV_(c) voltage 221 through the summing node 360, so ΔV_(c) can quickly respond to changes in the input voltage V_(in) 102 without waiting from the change pump circuit 301 to respond. The feedforward path makes the control switch 108 settle into ZVS condition more quickly, and saves the tuning range of the charge pump circuit 301 for compensating other parameter variations.

The counting circuit 315 records the number of consecutive times the voltage of the tuning capacitor 350 has been increased or decreased. If the voltage of the tuning capacitor 350 has been changed consecutively a number of times in either direction, the counter circuit 315 will increase the pulse width of the one-shot circuit 310. When PWMH signal 130 is disabled or controller restarts, a reset switch 355 is closed resetting the voltage of the tuning capacitor 350 to 0 v. This implementation of the T_(DM) optimizer 204 benefits from having only a single charge pump which allows for both scalability and fast tuning because the pulse width of the one-shot circuit 320 is easily programmed and tuned.

FIG. 4 illustrates a schematic block diagram of the T_(D(H-L)) optimizer 205 of FIG. 2. The T_(D(H-L)) optimizer 205 acts as a control circuit that implements a piece-wise linear function and includes a comparator 405 coupled to an OR gate 410 for setting the PWML signal 130 logic HIGH. The OR gate 410 is also coupled to the ZVS sensing circuit 206. The output of the comparator 405, TIO logic signal 209, is also coupled to the T_(DM) optimizer 204 for determining the adjustment of ΔV_(c) 221. The OR gate 410 will drive the PWML signal 130 to a logic HIGH state by outputting a logic HIGH signal to set the SR flip-flop 208. The output of the OR gate 410 will become logic HIGH when either the ZVS sensing circuit 206 determines that the switching node voltage V_(sw) 114 has reached 0V or the output of the comparator 405 is logic HIGH.

The comparator 405 determines if a value of a voltage value stored across a capacitor 421 is greater than a voltage value determined by a current subtraction circuit. The voltage stored across the capacitor C_(r) 421 is determined by a current i_(r) 441 output from current mirror 420. The current mirror 420 mirrors the current i_(r) 440 flowing through the transistor 434. The current i_(r) 440 is determined by the voltage V_(SET) 430 and resistance R_(SET) 435. The amplifier 432, as illustrated in FIG. 4, is configured to reflect the voltage V_(SET) 430 across the resistance R_(SET) 435. The resistance R_(SET) 435 may be a static resistance provided by, for example, a resistor or a variable resistance provided by, for example, a digital potentiometer.

Charging the capacitor C_(r) 421 is controlled by a charging switch Q_(r) 422. The charging switch Q_(r) will open, allowing the capacitor C_(r) 421 to charge when the logic circuit 415 detects that the PWMH signal transitions from a logic HIGH state to a logic LOW state. The capacitor C_(r) 421 will continue to charge until the voltage across the capacitor C_(r) 421 is greater than the voltage determined by the current subtraction circuit.

The current subtraction circuit includes a summing resistor R_(SUM) 423 coupled to a voltage supply V_(r) 424 and a diode 425. The diode outputs the difference between a pre-set current I_(th(Tz)) 426 and a current I_(VSL) 427 to the summing resistor R_(SUM) 423. The current I_(VSL) 427 is controlled by the output of V_(in) sensing circuit 203. When V_(in) sensing circuit 203 senses the V_(in) 102 changes through the negative winding voltage V_(AUX) 220, the current I_(VSL) 427 follows, so it provides a V_(in) feedforward signal to vary the dead time width of T_(D(H-L)) width in wide input voltage range. As such, T_(D(H-L))—the amount of time the capacitor C_(r) 421 is allowed to charge—is determined by the piece-wise linear function of equation (8) below.

If  I_(VSL) > I_(th(Tz)), T_(D(H − L)) = T_(SET) ${{{If}\mspace{14mu} I_{VSL}} < I_{{th}{({Tz})}}},{T_{D{({H - L})}} = {\frac{V_{r} + {R_{sum}\left( {I_{{th}{({Tz})}} - I_{VSL}} \right)}}{V_{SET}/R_{SET}}C_{r}}}$ ${where},{{T_{{SET}\mspace{14mu}}{programed}\mspace{14mu}{by}\mspace{14mu} R_{SET}} = \frac{V_{SET}T_{SET}}{C_{r}V_{r}}}$

This piece-wise linear implementation approximates the optimal value of T_(D(H-L)) over a useful input voltage range and avoids increased MCU cost by eliminating complex mathematical computation.

When the OR gate 410 outputs logic HIGH, causing the PWML signal 130 to be driven logic HIGH, the logic circuit 415 closes the charging switch Q_(r) 422 discharging the capacitor C_(r) 421 to ground.

FIG. 5 illustrates a schematic block diagram of the T_(D(L-H)) optimizer of FIG. 2. The T_(D(L-H)) optimizer circuit includes an AND gate 520 coupled to a comparator 530 and a one-shot delay circuit 528. The zero-crossing detection (ZCD) comparator 530 outputs logic HIGH when the auxiliary winding voltage V_(aux) 220 is greater than a zero-crossing detection voltage V_(ZCD) 505. When the output comparator 530 and the complement of the PWML signal 510 are both logic high, the AND gate 520 outputs a logic HIGH signal to set the SR flip-flop 207. The output to the SR flip-flop 207 is delayed for a variable dead time by the zero-crossing detection comparator 530 and the additional one-shot delay circuit 528. The zero-crossing of the aux winding voltage is used to provide a real-time indication that the switching node voltage 114 has been overcome in the slow ramping region caused by the high capacitance of the control switch 108 and increased to a high voltage level, so the complex calculation in Equation (4) or (5) can be avoided.

Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the scope of the disclosure. For example, although the above description is made in the context of a flyback converter circuit, the same teachings are applicable to other converter circuits. Such modifications, alterations, and combinations are to be viewed as being within the ambit of the present disclosure. 

What is claimed is:
 1. An apparatus comprising: a first timing circuit with at least one input configured to receive a first input from at least one first sensing circuit for a converter circuit; a second timing circuit with at least one input configured to receive a second input from at least one second sensing circuit for the converter circuit; a first state register connected to receive a first timing circuit output from the first timing circuit and having a first state register high state and a first state register low state and configured to output the first state register high state or the first state register low state for switching only a low-side switch of the converter circuit; and a second state register connected to receive a second timing circuit output from the second timing circuit and having a second state register high state and a second state register low state and configured to output the second state register high state or the second state register low state for switching only a high-side switch of the converter circuit.
 2. The apparatus of claim 1 wherein: the first timing circuit is configured to modify a first dead time between the high-side switch's turning off and the low-side switch's turning on; the second timing circuit is configured to modify a second dead time between the low-side switch's turning off and the high-side switch's turning on.
 3. The apparatus of claim 2, wherein the first timing circuit is configured to modify the first dead time between turning off the high-side switch and turning on the low-side switch according to a piece-wise linear function.
 4. The apparatus of claim 2, wherein the apparatus is configured to control the low-side switch and the high-side switch according to the switching voltage in each switching cycle.
 5. The apparatus of claim 1 further comprising a third timing circuit with at least one input configured to receive the first input from the at least one first sensing circuit and wherein the second state register is connected to receive a reset signal based at least in part on a value of a third timing circuit output signal and to output the second state register high state or the second state register low state based on the reset signal and the second timing circuit output.
 6. The apparatus of claim 5 wherein the third timing circuit is configured to modify a length of on-time for the high-side switch.
 7. The apparatus of claim 5, wherein the second state register is configured to be controlled to the second state register low state in response to the reset signal.
 8. The apparatus of claim 7, wherein the second state register is configured to be controlled to the second state register low state based on a comparison between a voltage determined, at least in part, by the value of the third timing circuit output signal and a voltage of a ramp function.
 9. The apparatus of claim 5, wherein the third timing circuit comprises: a tuning polarity and speed control circuit configured to determine to increase or decrease the value of the third timing circuit output signal, and a charge pump circuit configured to increase or decrease the value of the third timing circuit output signal.
 10. The apparatus of claim 9, wherein the tuning and polarity control circuit comprises a counting circuit configured to increase a rate of increase or decrease of the value of the third timing circuit output signal based on a number of times the value of the third timing circuit output signal has been consecutively increased or decreased.
 11. The apparatus of claim 5, wherein the third timing circuit is configured to increase or decrease the value of the third timing circuit output to adjust when the high-side switch is turned off in a current switching cycle according to a switching voltage in a previous switching cycle.
 12. The apparatus of claim 1 further comprising the converter circuit, which comprises a flyback converter circuit comprising the low-side switch and the high-side switch.
 13. The apparatus of claim 12, wherein the flyback converter circuit further comprises: an auxiliary winding configured to produce an auxiliary voltage corresponding to a present input voltage for the flyback converter circuit's primary side, and a switching node having a switching node voltage.
 14. The apparatus of claim 13, wherein the at least one first sensing circuit comprises an input voltage sensing circuit configured to determine an input voltage of the flyback converter circuit based on the auxiliary voltage.
 15. The apparatus of claim 14, further comprising a third timing circuit with at least one input configured to receive the first input from the at least one first sensing circuit and wherein the second state register is connected to receive a reset signal based at least in part on a value of a third timing circuit output signal and to output the second state register high state or the second state register low state based on the reset signal and the second timing circuit output, wherein the third timing circuit is configured to feedforward the input voltage of the flyback converter circuit as at least part of the value of the third timing circuit output.
 16. The apparatus of claim 15 wherein the at least one first sensing circuit comprises a zero-voltage detection circuit configured to generate a zero-voltage signal in response to a zero-voltage condition of a switching voltage for the flyback converter circuit, and wherein the third timing circuit is configured to adjust the value of the third timing circuit output based at least in part on the zero-voltage signal.
 17. The apparatus of claim 13, wherein the first timing circuit is configured to modify a first dead time between the high-side switch's turning off and the low-side switch's turning on according to a piece-wise linear function based at least in part on the auxiliary voltage and the switching voltage.
 18. The apparatus of claim 17, wherein the first timing circuit comprises: a current subtraction circuit configured to output a current difference between a pre-set current I_(th(Tz)) and a current I_(VSL) corresponding to the present input voltage, a summing resistor having a resistance value of R_(SUM) and coupled to a voltage supply V_(r) and to receive the current difference from the current subtraction circuit, a transistor having a gate connected to receive a voltage based on a comparison between a set voltage V_(SET) and a voltage across a set resistance R_(SET), wherein the voltage across the set resistance is based on a transistor current flowing through the resistance, a capacitor having a capacitance C_(r) coupled to receive a current equivalent to the transistor current, and wherein the first timing circuit is configured to modify the first dead time by providing an output T_(D(H-L)) according to the niece-wise linear function defined as: If  I_(VSL) > I_(th(Tz)), T_(D(H − L)) = T_(SET) ${{{If}\mspace{14mu} I_{VSL}} < I_{{th}{({Tz})}}},{T_{D{({H - L})}} = {\frac{V_{r} + {R_{sum}\left( {I_{{th}{({Tz})}} - I_{VSL}} \right)}}{V_{SET}/R_{SET}}C_{r}}}$ ${where},{{T_{{SET}\mspace{14mu}}{programed}\mspace{14mu}{by}\mspace{14mu} R_{SET}} = {\frac{V_{SET}T_{SET}}{C_{r}V_{r}}.}}$
 19. An apparatus comprising: an active clamp flyback converter comprising a high-side switch and a low-side switch; a control circuit comprising a first timing circuit, a second timing circuit, a third timing circuit, a first state register, and a second state register, wherein the first state register's output is coupled to control the low-side switch, and the second state register's output is coupled to control the high-side switch, and wherein the second timing circuit and the third timing circuits are coupled to the second state register to control the second state register's output and the first timing circuit is coupled to the first state register to control the first state register's output. 